CI
ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
Cisco · Pune
वेतनवेतन नहीं लिखा
कहाँPuneMaharashtra
प्रकारFull time
Posted25 Sep18 दिन पहले, Adzuna से
Kaam ने check किया
Fee, deposit या पैसे माँगने के निशान नहीं
अच्छी English चाहिए, बोलने और लिखने में
दिन का काम
गाड़ी या licence नहीं चाहिए
इस job के बारे में
Meet the Team Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions…
ऐसी jobsसब देखो →
ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12 years, BangaloreCisco · BangaloreAdzuna से
Leader, ASIC Engineering | RTL, Datapath, Network Processing UnitCisco · BangaloreAdzuna से
Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 yearsCisco · BangaloreAdzuna से
काम पाने के लिए कभी पैसे मत दो। Fee माँगे तो scam है। दस निशान →