ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM
Cisco India · Pune) · Pune
PayPay not listed
WherePuneMaharashtra
TypeFull time
Posted22 May165 days ago, from the company site
About this job
We are recruiting a ASIC Engineering Design Verification Leader to drive the design and verification of advanced optical transceivers and platforms for Cisco's data centre networking solutions. Lead verification documentation, develop testbench components, and collaborate with multidisciplinary teams. Ideal for experienced engineers with strong expertise in SystemVerilog, Python, C, and UVM.
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