Staff/Senior Staff Physical Design Engineer (Technical Lead)

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Title

Staff/Senior Staff Physical Design Engineer (Technical Lead)

Experience

Staff 8-10 years

Senior Staff 11-13 years

Location

Bangalore Hybrid/Remote or Remote in IndiaThe Role

We are seeking a high-impactStaff/Senior Staff Physical Design Engineer to serve as a Technical Lead for our next-generation silicon products.This is a "player-coach" role designed for aversatile expertwho is equally comfortable architecting a convergence strategy as they are mentoring a small team of engineers.You will own the physical delivery of a major sub-chip or complex block, pushing the absolute limits ofPPA (Power, Performance, Area).As a Staff/Senior Staff lead, you are expected to be the "anchor" of the project—assertive in your decision-making, highly analytical in your debugging, and adept at managing stakeholders to ensure we hit our tape-out milestones without compromise.Key Responsibilities

Technical Leadership: Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub-chip or partition.

    SOC clocking , FEV/VCLP specialized skills are preferred.

Complex Block/Sub-chip Ownership: Take personal hands-on ownership of the most critical, high-congestion, or timing-critical blocks in the design.

Timing & PPA Strategy: Act as the primary architect for PD convergence. Derive and implement custom "PPA recipes" that go beyond standard vendor flows to meet aggressive targets.

Advanced Automation: Drive efficiency across the team by developing sophisticatedTcl and Python scripts for flow automation, data mining, and sign-off verification.

Stakeholder Management: Build strong rapport with RTL, DFT, and Synthesis teams. Effectively communicate risks and push for "left-shift" optimizations to safeguard the project schedule.

Sign-off Accountability: Ensure the sub-chip meets all gold-standard sign-off criteria, including STA, EM/IR (Voltus/Apache), and Physical Verification (Pegasus/Calibre).

Technical Requirements

Category

Requirement

Experience

Staff 8-10 yearsSenior Staff 11-13 yearsPD experience with a proven track record of multiple successfullead-level tape-outs.Tool Mastery

Expert-level proficiency inCadence Innovus/Tempus

Timing Convergence

Deep expertise in Static Timing Analysis (STA), including complex clocking, multi-corner sign-off, and crosstalk closure.PPA Optimization

Demonstrated ability to squeeze performance out of advanced nodes (7nm, 5nm, or below) via custom floorplanning, CTS strategies and other convergence approaches.Automation

Advanced scripting inTcl and Python to build scalable, repeatable design methodologies.Leadership & Soft Skills

High Workability & Assertiveness: You are a proactive communicator who can hold ground on technical requirements while remaining collaborative and solution-oriented.

Analytical Problem Solver: You don't just identify violations; you analyze the "why" and derive a systemic fix that prevents the issue from recurring.

Driven & Versatile: You possess the "Senior Staff" mindset—ready to jump into any part of the flow (from floorplan to GDSII) to unblock the team and meet the schedule.

Mentorship

Passionate about raising the technical bar for the engineers reporting to you.

Originally posted on Himalayas